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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [core/] - Rev 39

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Rev	Log message	Author	Age	Path
14	changed comments, file is now according to OC design rules	JonasDC	4306d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4306d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
12	updated comments, file is now completely according to design rules	JonasDC	4306d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
10	changed signal input port names to correct name	JonasDC	4306d 13h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4306d 13h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
8	added descriptive comments	JonasDC	4306d 15h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4306d 15h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4306d 16h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4306d 18h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4307d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/

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