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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 63

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Rev	Log message	Author	Age	Path
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4291d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4291d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4292d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4292d 02h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4292d 07h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4292d 07h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4292d 21h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4296d 06h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
23	added descriptive comments	JonasDC	4296d 07h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4299d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/

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