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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [core/] - Rev 92

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32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4252d 19h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4253d 00h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4253d 01h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4253d 15h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4257d 00h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
23 added descriptive comments JonasDC 4257d 01h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4259d 18h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
21 changed x_i signal to xi JonasDC 4261d 02h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4261d 02h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4265d 21h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/

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