URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] - Rev 93

Rev	Log message	Author	Age	Path
61	updated comments, added optional altera constraint	JonasDC	4171d 08h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4173d 22h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4173d 23h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
55	updated resource usage in comments	JonasDC	4177d 22h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4177d 23h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
53	correctly inferred ram for altera dual port ram	JonasDC	4178d 05h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
52	correct inferring of blockram, no additional resources.	JonasDC	4178d 06h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
51	true dual port ram for xilinx	JonasDC	4178d 06h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4178d 06h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4258d 06h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/