URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] - Rev 54

Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4265d 06h	/mod_sim_exp/tags/Release_1.5/rtl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4268d 15h	/mod_sim_exp/tags/Release_1.5/rtl/
23	added descriptive comments	JonasDC	4268d 16h	/mod_sim_exp/tags/Release_1.5/rtl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4271d 10h	/mod_sim_exp/tags/Release_1.5/rtl/
21	changed x_i signal to xi	JonasDC	4272d 18h	/mod_sim_exp/tags/Release_1.5/rtl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4272d 18h	/mod_sim_exp/tags/Release_1.5/rtl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4277d 13h	/mod_sim_exp/tags/Release_1.5/rtl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4278d 13h	/mod_sim_exp/tags/Release_1.5/rtl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4278d 18h	/mod_sim_exp/tags/Release_1.5/rtl/
16	package with modified generic parameter for register_n	JonasDC	4279d 07h	/mod_sim_exp/tags/Release_1.5/rtl/