URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] - Rev 84

Rev	Log message	Author	Age	Path
52	correct inferring of blockram, no additional resources.	JonasDC	4165d 19h	/mod_sim_exp/tags/Release_1.5/rtl/
51	true dual port ram for xilinx	JonasDC	4165d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4165d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4245d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4249d 13h	/mod_sim_exp/tags/Release_1.5/rtl/
43	made the core parameters generics	JonasDC	4249d 13h	/mod_sim_exp/tags/Release_1.5/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4255d 21h	/mod_sim_exp/tags/Release_1.5/rtl/
41	removed deprecated files from version control	JonasDC	4255d 21h	/mod_sim_exp/tags/Release_1.5/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4264d 01h	/mod_sim_exp/tags/Release_1.5/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4264d 12h	/mod_sim_exp/tags/Release_1.5/rtl/