URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 87

Rev	Log message	Author	Age	Path
64	added synthesis reports of xilinx and altera	JonasDC	4128d 02h	/mod_sim_exp/trunk/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4128d 02h	/mod_sim_exp/trunk/
62	not used anymore	JonasDC	4128d 05h	/mod_sim_exp/trunk/
61	updated comments, added optional altera constraint	JonasDC	4128d 05h	/mod_sim_exp/trunk/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4130d 19h	/mod_sim_exp/trunk/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4130d 20h	/mod_sim_exp/trunk/
55	updated resource usage in comments	JonasDC	4134d 19h	/mod_sim_exp/trunk/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4134d 19h	/mod_sim_exp/trunk/
53	correctly inferred ram for altera dual port ram	JonasDC	4135d 02h	/mod_sim_exp/trunk/
52	correct inferring of blockram, no additional resources.	JonasDC	4135d 02h	/mod_sim_exp/trunk/