URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 82

Rev	Log message	Author	Age	Path
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4126d 05h	/mod_sim_exp/trunk/rtl/vhdl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4206d 05h	/mod_sim_exp/trunk/rtl/vhdl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4209d 23h	/mod_sim_exp/trunk/rtl/vhdl/
43	made the core parameters generics	JonasDC	4209d 23h	/mod_sim_exp/trunk/rtl/vhdl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4216d 07h	/mod_sim_exp/trunk/rtl/vhdl/
41	removed deprecated files from version control	JonasDC	4216d 07h	/mod_sim_exp/trunk/rtl/vhdl/
40	adjusted core instantiation to new core module name	JonasDC	4224d 11h	/mod_sim_exp/trunk/rtl/vhdl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4224d 22h	/mod_sim_exp/trunk/rtl/vhdl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4225d 04h	/mod_sim_exp/trunk/rtl/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4229d 01h	/mod_sim_exp/trunk/rtl/vhdl/