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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 94

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Rev	Log message	Author	Age	Path
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4222d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4226d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4227d 00h	/mod_sim_exp/trunk/rtl/vhdl/core/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4227d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4227d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4227d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4227d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4227d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4228d 03h	/mod_sim_exp/trunk/rtl/vhdl/core/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4231d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/

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