URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 196

Rev	Log message	Author	Age	Path
176	Fixed documentation errors, Modified uSec_Tick such that it is always generated regardless of the interval.	jshamlet	2908d 06h	/open8_urisc/
175	Added 4 and 8-bit LCD interfaces with backlight and contrast DACs	jshamlet	2908d 11h	/open8_urisc/
174	Added ROM/RAM wrappers	jshamlet	3103d 05h	/open8_urisc/
173	Added a couple of useful interfaces for detecting button presses and clock changes.	jshamlet	3103d 06h	/open8_urisc/
172	General code cleanup	jshamlet	3103d 06h	/open8_urisc/
171	Fixed comments for offsets 0x0 - 0x3 to indicate the read value	jshamlet	3103d 06h	/open8_urisc/
170	Added 24-bit resolution epoch timer / alarm clock	jshamlet	3103d 06h	/open8_urisc/
169	Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules.	jshamlet	3158d 07h	/open8_urisc/
168	Simplified write data path logic, Converted RTC to packed BCD, Corrected several bugs in real time clock component,	jshamlet	3937d 03h	/open8_urisc/
167	Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow. Added several useful modules that use the Open8 bus.	jshamlet	3945d 01h	/open8_urisc/