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[/] [open8_urisc/] - Rev 222

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Rev Log message Author Age Path
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.
jshamlet 1606d 15h /open8_urisc/
201 Fixed comments regarding RX Checksum location jshamlet 1608d 13h /open8_urisc/
200 Renamed dual-port buffer to match other entities. jshamlet 1608d 13h /open8_urisc/
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1608d 13h /open8_urisc/
198 Removed debugging memory jshamlet 1608d 21h /open8_urisc/
197 Fixed incorrect comments jshamlet 1608d 21h /open8_urisc/
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1608d 22h /open8_urisc/
195 Added dual-port RAM core for SDLC interface. jshamlet 1609d 17h /open8_urisc/
194 Cleaned up licensing sections jshamlet 1609d 17h /open8_urisc/
193 Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. jshamlet 1609d 17h /open8_urisc/

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