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[/] [open8_urisc/] - Rev 234

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Rev Log message Author Age Path
214 Initial add of some older code jshamlet 1580d 20h /open8_urisc/
213 Code and comment cleanup jshamlet 1580d 21h /open8_urisc/
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1581d 03h /open8_urisc/
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1582d 00h /open8_urisc/
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1582d 03h /open8_urisc/
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1582d 15h /open8_urisc/
208 Removed unnecessary package references jshamlet 1583d 01h /open8_urisc/
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1583d 18h /open8_urisc/
206 Merged interrupt logic with other clocked process. jshamlet 1587d 13h /open8_urisc/
205 More code and comment cleanup for the new SDLC engine jshamlet 1587d 13h /open8_urisc/

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