URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 239

Rev	Log message	Author	Age	Path
219	Added revision block and corrected creation date.	jshamlet	1584d 12h	/open8_urisc/
218	Revision sections added, vdsm8.vhd added.	jshamlet	1584d 12h	/open8_urisc/
217	Broke out the vdsm8 as a separate entity, since it is used in several places, Even MORE code cleanup.	jshamlet	1584d 13h	/open8_urisc/
216	Fixed missing parenthesis	jshamlet	1584d 15h	/open8_urisc/
215	More code cleanup	jshamlet	1584d 15h	/open8_urisc/
214	Initial add of some older code	jshamlet	1588d 13h	/open8_urisc/
213	Code and comment cleanup	jshamlet	1588d 14h	/open8_urisc/
212	Fixed issue with rewritten epoch timer not clearing alarm on set point write.	jshamlet	1588d 20h	/open8_urisc/
211	Ok, this time with feeling. Timer should now properly reset on interval update.	jshamlet	1589d 17h	/open8_urisc/
210	Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts. Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted. Lastly, added the I bit to the exported flags for possible use in memory protection schemes.	jshamlet	1589d 20h	/open8_urisc/