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Rev Log message Author Age Path
249 Added a 32-bit wide register and split the status_led core from o8_status_led.vhd, allowing it to be used as a subcomponent elsewhere. jshamlet 1525d 21h /open8_urisc/
248 Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. jshamlet 1526d 05h /open8_urisc/
247 Fixed problem where parallel interface was always forcing the data registers due to bad alias. jshamlet 1526d 22h /open8_urisc/
246 The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.

The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces.		 jshamlet 1527d 03h /open8_urisc/
245 Modified the CPU's Supervisor_Mode to also protect SMSK and RSP instructions,
Added an external interrupt manager, o8_int_mgr.vhd.		 jshamlet 1529d 02h /open8_urisc/
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.		 jshamlet 1529d 23h /open8_urisc/
243 Optimized code to prefer RAM vs register. jshamlet 1537d 02h /open8_urisc/
242 Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.

Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior.		 jshamlet 1537d 02h /open8_urisc/
241 Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. jshamlet 1541d 22h /open8_urisc/
240 Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. jshamlet 1544d 01h /open8_urisc/

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