URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 282

Rev	Log message	Author	Age	Path
262	Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map.	jshamlet	1446d 02h	/open8_urisc/
261	Increased delay timer to 7 bits for button press detection.	jshamlet	1453d 02h	/open8_urisc/
260	Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations.	jshamlet	1466d 01h	/open8_urisc/
259	Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE, Added a pulse interval measurement entity, Fixed comments.	jshamlet	1466d 02h	/open8_urisc/
258	Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity.	jshamlet	1467d 00h	/open8_urisc/
257	Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches.	jshamlet	1467d 01h	/open8_urisc/
256	Removed unused generic from the status_led.vhd and cleaned up comments on the CPU	jshamlet	1467d 02h	/open8_urisc/
255	Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic.	jshamlet	1467d 06h	/open8_urisc/
254	Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed.	jshamlet	1467d 21h	/open8_urisc/
253	Fixed spelling error in comment	jshamlet	1467d 21h	/open8_urisc/