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[/] [open8_urisc/] [trunk/] - Rev 232

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Rev Log message Author Age Path
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1523d 17h /open8_urisc/trunk/
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1524d 15h /open8_urisc/trunk/
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1524d 18h /open8_urisc/trunk/
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1525d 06h /open8_urisc/trunk/
208 Removed unnecessary package references jshamlet 1525d 16h /open8_urisc/trunk/
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1526d 09h /open8_urisc/trunk/
206 Merged interrupt logic with other clocked process. jshamlet 1530d 04h /open8_urisc/trunk/
205 More code and comment cleanup for the new SDLC engine jshamlet 1530d 04h /open8_urisc/trunk/
204 Fixed more incorrect comments jshamlet 1530d 04h /open8_urisc/trunk/
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1530d 10h /open8_urisc/trunk/

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