URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 185

Rev	Log message	Author	Age	Path
155	Fixed additional interrupt logic bug, Optimized several blocks - including ALU, stack, program counter, and data path.	jshamlet	4718d 06h	/open8_urisc/trunk/VHDL/
154	Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed.	jshamlet	4723d 09h	/open8_urisc/trunk/VHDL/
153	Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded, Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.	jshamlet	4750d 05h	/open8_urisc/trunk/VHDL/
151	Fixed STO instruction and interrupt logic to avoid address bus corruption issues.	jshamlet	4760d 08h	/open8_urisc/trunk/VHDL/
10	corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values	khays	4901d 17h	/open8_urisc/trunk/VHDL/
8	Need to learn SVN...	jshamlet	5230d 04h	/open8_urisc/trunk/VHDL/
7	Initial Upload	jshamlet	5230d 04h	/open8_urisc/trunk/open8_urisc/VHDL/