URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 203

Rev	Log message	Author	Age	Path
183	Renamed core to o8_cpu to match new naming scheme	jshamlet	1602d 18h	/open8_urisc/trunk/VHDL/
182	Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled.	jshamlet	1602d 18h	/open8_urisc/trunk/VHDL/
181	Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic.	jshamlet	1603d 14h	/open8_urisc/trunk/VHDL/
180	Added additional Open8 compatible modules	jshamlet	1607d 18h	/open8_urisc/trunk/VHDL/
177	Fixed comments in RTC module	jshamlet	2927d 19h	/open8_urisc/trunk/VHDL/
176	Fixed documentation errors, Modified uSec_Tick such that it is always generated regardless of the interval.	jshamlet	2932d 16h	/open8_urisc/trunk/VHDL/
175	Added 4 and 8-bit LCD interfaces with backlight and contrast DACs	jshamlet	2932d 21h	/open8_urisc/trunk/VHDL/
174	Added ROM/RAM wrappers	jshamlet	3127d 16h	/open8_urisc/trunk/VHDL/
173	Added a couple of useful interfaces for detecting button presses and clock changes.	jshamlet	3127d 16h	/open8_urisc/trunk/VHDL/
172	General code cleanup	jshamlet	3127d 16h	/open8_urisc/trunk/VHDL/