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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 219

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Rev Log message Author Age Path
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1530d 10h /open8_urisc/trunk/VHDL/
198 Removed debugging memory jshamlet 1530d 18h /open8_urisc/trunk/VHDL/
197 Fixed incorrect comments jshamlet 1530d 18h /open8_urisc/trunk/VHDL/
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1530d 19h /open8_urisc/trunk/VHDL/
195 Added dual-port RAM core for SDLC interface. jshamlet 1531d 14h /open8_urisc/trunk/VHDL/
194 Cleaned up licensing sections jshamlet 1531d 14h /open8_urisc/trunk/VHDL/
193 Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. jshamlet 1531d 14h /open8_urisc/trunk/VHDL/
192 Added SDLC packet engine jshamlet 1531d 14h /open8_urisc/trunk/VHDL/
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1531d 15h /open8_urisc/trunk/VHDL/
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.		 jshamlet 1543d 12h /open8_urisc/trunk/VHDL/

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