URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 221

Rev	Log message	Author	Age	Path
201	Fixed comments regarding RX Checksum location	jshamlet	1554d 14h	/open8_urisc/trunk/VHDL/
200	Renamed dual-port buffer to match other entities.	jshamlet	1554d 15h	/open8_urisc/trunk/VHDL/
199	Added monitor ram for debugging and fixed issue with dual-port read path.	jshamlet	1554d 15h	/open8_urisc/trunk/VHDL/
198	Removed debugging memory	jshamlet	1554d 23h	/open8_urisc/trunk/VHDL/
197	Fixed incorrect comments	jshamlet	1554d 23h	/open8_urisc/trunk/VHDL/
196	Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored)	jshamlet	1555d 00h	/open8_urisc/trunk/VHDL/
195	Added dual-port RAM core for SDLC interface.	jshamlet	1555d 18h	/open8_urisc/trunk/VHDL/
194	Cleaned up licensing sections	jshamlet	1555d 18h	/open8_urisc/trunk/VHDL/
193	Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation.	jshamlet	1555d 19h	/open8_urisc/trunk/VHDL/
192	Added SDLC packet engine	jshamlet	1555d 19h	/open8_urisc/trunk/VHDL/