URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 224

Rev	Log message	Author	Age	Path
204	Fixed more incorrect comments	jshamlet	1605d 13h	/open8_urisc/trunk/VHDL/
203	Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal.	jshamlet	1605d 19h	/open8_urisc/trunk/VHDL/
202	Fixed receiver bug that caused false flag detection, Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.	jshamlet	1605d 19h	/open8_urisc/trunk/VHDL/
201	Fixed comments regarding RX Checksum location	jshamlet	1607d 17h	/open8_urisc/trunk/VHDL/
200	Renamed dual-port buffer to match other entities.	jshamlet	1607d 17h	/open8_urisc/trunk/VHDL/
199	Added monitor ram for debugging and fixed issue with dual-port read path.	jshamlet	1607d 17h	/open8_urisc/trunk/VHDL/
198	Removed debugging memory	jshamlet	1608d 01h	/open8_urisc/trunk/VHDL/
197	Fixed incorrect comments	jshamlet	1608d 01h	/open8_urisc/trunk/VHDL/
196	Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored)	jshamlet	1608d 02h	/open8_urisc/trunk/VHDL/
195	Added dual-port RAM core for SDLC interface.	jshamlet	1608d 21h	/open8_urisc/trunk/VHDL/