URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 227

Rev	Log message	Author	Age	Path
207	Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics.	jshamlet	1541d 06h	/open8_urisc/trunk/VHDL/
206	Merged interrupt logic with other clocked process.	jshamlet	1545d 01h	/open8_urisc/trunk/VHDL/
205	More code and comment cleanup for the new SDLC engine	jshamlet	1545d 01h	/open8_urisc/trunk/VHDL/
204	Fixed more incorrect comments	jshamlet	1545d 02h	/open8_urisc/trunk/VHDL/
203	Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal.	jshamlet	1545d 08h	/open8_urisc/trunk/VHDL/
202	Fixed receiver bug that caused false flag detection, Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.	jshamlet	1545d 08h	/open8_urisc/trunk/VHDL/
201	Fixed comments regarding RX Checksum location	jshamlet	1547d 06h	/open8_urisc/trunk/VHDL/
200	Renamed dual-port buffer to match other entities.	jshamlet	1547d 06h	/open8_urisc/trunk/VHDL/
199	Added monitor ram for debugging and fixed issue with dual-port read path.	jshamlet	1547d 06h	/open8_urisc/trunk/VHDL/
198	Removed debugging memory	jshamlet	1547d 14h	/open8_urisc/trunk/VHDL/