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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 262

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242 Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.

Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior.		 jshamlet 1550d 22h /open8_urisc/trunk/VHDL/
241 Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. jshamlet 1555d 17h /open8_urisc/trunk/VHDL/
240 Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. jshamlet 1557d 21h /open8_urisc/trunk/VHDL/
231 Updated sample projects and added elapsed time capture (chronometer) module jshamlet 1573d 01h /open8_urisc/trunk/VHDL/
229 Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. jshamlet 1576d 22h /open8_urisc/trunk/VHDL/
228 Added an initialization constant for the OPEN8_BUS_TYPE record. jshamlet 1577d 12h /open8_urisc/trunk/VHDL/
227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1577d 19h /open8_urisc/trunk/VHDL/
226 Forgot the updated package file... jshamlet 1577d 23h /open8_urisc/trunk/VHDL/
225 Added Halt_Ack to go with Halt_Req. jshamlet 1577d 23h /open8_urisc/trunk/VHDL/
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1578d 01h /open8_urisc/trunk/VHDL/

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