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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 263

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Rev Log message Author Age Path
243 Optimized code to prefer RAM vs register. jshamlet 1504d 10h /open8_urisc/trunk/VHDL/
242 Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.

Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior.		 jshamlet 1504d 11h /open8_urisc/trunk/VHDL/
241 Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. jshamlet 1509d 06h /open8_urisc/trunk/VHDL/
240 Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. jshamlet 1511d 10h /open8_urisc/trunk/VHDL/
231 Updated sample projects and added elapsed time capture (chronometer) module jshamlet 1526d 14h /open8_urisc/trunk/VHDL/
229 Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. jshamlet 1530d 11h /open8_urisc/trunk/VHDL/
228 Added an initialization constant for the OPEN8_BUS_TYPE record. jshamlet 1531d 01h /open8_urisc/trunk/VHDL/
227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1531d 08h /open8_urisc/trunk/VHDL/
226 Forgot the updated package file... jshamlet 1531d 12h /open8_urisc/trunk/VHDL/
225 Added Halt_Ack to go with Halt_Req. jshamlet 1531d 12h /open8_urisc/trunk/VHDL/

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