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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 277

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255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1462d 00h /open8_urisc/trunk/VHDL/
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1462d 15h /open8_urisc/trunk/VHDL/
253 Fixed spelling error in comment jshamlet 1462d 15h /open8_urisc/trunk/VHDL/
252 (This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.		 jshamlet 1462d 15h /open8_urisc/trunk/VHDL/
251 Added RAM write fault detection, which can be used to indicate a memory write violation by the CPU. This allows a clean shutdown in the event of a memory problem/program crash.

Fixed a bug in the status_led.vhd entity that kept the flashing light function from working. The new code uses a maximal length 24-bit LFSR to create long delays. This is more efficient than a binary counter, but results in non-exact frequencies as a function of SYSTEM_FREQUENCY / (2^24-1).

Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.		 jshamlet 1462d 15h /open8_urisc/trunk/VHDL/
250 Removed monitor RAM from SDLC model, as it is now proven to work. jshamlet 1466d 23h /open8_urisc/trunk/VHDL/
249 Added a 32-bit wide register and split the status_led core from o8_status_led.vhd, allowing it to be used as a subcomponent elsewhere. jshamlet 1478d 15h /open8_urisc/trunk/VHDL/
248 Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. jshamlet 1478d 23h /open8_urisc/trunk/VHDL/
247 Fixed problem where parallel interface was always forcing the data registers due to bad alias. jshamlet 1479d 16h /open8_urisc/trunk/VHDL/
246 The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.

The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces.		 jshamlet 1479d 21h /open8_urisc/trunk/VHDL/

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