OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 287

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1427d 08h /open8_urisc/trunk/VHDL/
264 Updated comments jshamlet 1437d 05h /open8_urisc/trunk/VHDL/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1437d 05h /open8_urisc/trunk/VHDL/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1446d 09h /open8_urisc/trunk/VHDL/
261 Increased delay timer to 7 bits for button press detection. jshamlet 1453d 09h /open8_urisc/trunk/VHDL/
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1466d 08h /open8_urisc/trunk/VHDL/
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.
jshamlet 1466d 09h /open8_urisc/trunk/VHDL/
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1467d 07h /open8_urisc/trunk/VHDL/
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1467d 08h /open8_urisc/trunk/VHDL/
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1467d 09h /open8_urisc/trunk/VHDL/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.