URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 301

Rev	Log message	Author	Age	Path
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1260d 13h	/open8_urisc/trunk/VHDL/
276	More comment fixes	jshamlet	1295d 16h	/open8_urisc/trunk/VHDL/
275	Fixed a minor comment error.	jshamlet	1297d 10h	/open8_urisc/trunk/VHDL/
274	Updated comments with more corrections	jshamlet	1297d 17h	/open8_urisc/trunk/VHDL/
273	Updated comments with corrections	jshamlet	1297d 19h	/open8_urisc/trunk/VHDL/
271	Removed deleted generic define.	jshamlet	1307d 18h	/open8_urisc/trunk/VHDL/
270	Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally. Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.	jshamlet	1307d 18h	/open8_urisc/trunk/VHDL/
269	Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance.	jshamlet	1310d 08h	/open8_urisc/trunk/VHDL/
268	Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL.	jshamlet	1310d 08h	/open8_urisc/trunk/VHDL/
267	Corrected the file description to indicate this is an example package.	jshamlet	1310d 08h	/open8_urisc/trunk/VHDL/