URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 308

Rev	Log message	Author	Age	Path
280	Got rid of silly aliases that connected the dual-port memory and the arbitration logic.	jshamlet	1274d 23h	/open8_urisc/trunk/VHDL/
279	More comment cleanup	jshamlet	1275d 20h	/open8_urisc/trunk/VHDL/
278	Flattened the SDLC interface to fewer files and eliminated the package file.	jshamlet	1276d 14h	/open8_urisc/trunk/VHDL/
276	More comment fixes	jshamlet	1311d 16h	/open8_urisc/trunk/VHDL/
275	Fixed a minor comment error.	jshamlet	1313d 10h	/open8_urisc/trunk/VHDL/
274	Updated comments with more corrections	jshamlet	1313d 17h	/open8_urisc/trunk/VHDL/
273	Updated comments with corrections	jshamlet	1313d 19h	/open8_urisc/trunk/VHDL/
271	Removed deleted generic define.	jshamlet	1323d 19h	/open8_urisc/trunk/VHDL/
270	Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally. Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.	jshamlet	1323d 19h	/open8_urisc/trunk/VHDL/
269	Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance.	jshamlet	1326d 08h	/open8_urisc/trunk/VHDL/