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29 Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator.		 dgisselq 2815d 17h /openarty/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2815d 18h /openarty/
27 Bus changes ... dgisselq 2815d 18h /openarty/
26 Adjusted the timing comments. dgisselq 2815d 18h /openarty/
25 The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v.		 dgisselq 2824d 02h /openarty/
24 Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board.		 dgisselq 2842d 22h /openarty/
23 Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later.		 dgisselq 2852d 21h /openarty/
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 2852d 21h /openarty/
21 Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus.		 dgisselq 2852d 21h /openarty/
20 Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before.		 dgisselq 2852d 21h /openarty/

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