URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] - Rev 50

Rev	Log message	Author	Age	Path
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2787d 06h	/openarty/
29	Here's the memory pin list, necessary for running Xilinx's Memory Interface Generator.	dgisselq	2815d 02h	/openarty/
28	Including the updates and corrections from the wbuart32 project.	dgisselq	2815d 03h	/openarty/
27	Bus changes ...	dgisselq	2815d 03h	/openarty/
26	Adjusted the timing comments.	dgisselq	2815d 03h	/openarty/
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2823d 11h	/openarty/
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2842d 07h	/openarty/
23	Includes settings necessary for the Arty to load from flash builds, and to reconfigure itself later.	dgisselq	2852d 06h	/openarty/
22	A useful script for programming the device, given that the current device program includes a valid comms interface.	dgisselq	2852d 06h	/openarty/
21	Removed the OLED controller one additional clock from the bus. This was necessary to maintain the 200MHz clock speed, especially given the growing fanout of the device bus.	dgisselq	2852d 06h	/openarty/