URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] - Rev 53

Rev	Log message	Author	Age	Path
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2797d 11h	/openarty/
32	Brought the CPU to its first working version, to include demo.	dgisselq	2798d 14h	/openarty/
31	Initial network is now working. Adding CPU control files to repository.	dgisselq	2799d 07h	/openarty/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2799d 07h	/openarty/
29	Here's the memory pin list, necessary for running Xilinx's Memory Interface Generator.	dgisselq	2827d 03h	/openarty/
28	Including the updates and corrections from the wbuart32 project.	dgisselq	2827d 04h	/openarty/
27	Bus changes ...	dgisselq	2827d 04h	/openarty/
26	Adjusted the timing comments.	dgisselq	2827d 04h	/openarty/
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2835d 12h	/openarty/
24	Here are the updates from the first (failed) attempt to try to integrate the DDR3 SDRAM controller onto this board.	dgisselq	2854d 08h	/openarty/