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[/] [openmsp430/] - Rev 129

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109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4836d 02h /openmsp430/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4837d 15h /openmsp430/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4837d 15h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4837d 16h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4852d 17h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4856d 18h /openmsp430/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4857d 23h /openmsp430/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4858d 16h /openmsp430/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4858d 18h /openmsp430/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4861d 17h /openmsp430/

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