URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] - Rev 51

Rev	Log message	Author	Age	Path
31	Update documentation (new Altera FPGA project + diverse minor updates)	olivier.girard	5306d 09h	/openmsp430/
30	Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution).	olivier.girard	5306d 10h	/openmsp430/
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5306d 11h	/openmsp430/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5314d 18h	/openmsp430/
27	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5314d 18h	/openmsp430/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5314d 18h	/openmsp430/
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5404d 16h	/openmsp430/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5404d 16h	/openmsp430/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5425d 14h	/openmsp430/
22	Updated some links in the HTML documentation.	olivier.girard	5438d 11h	/openmsp430/