URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] - Rev 60

Rev	Log message	Author	Age	Path
40	Minor updates.	olivier.girard	5325d 16h	/openmsp430/
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5325d 16h	/openmsp430/
38	Remove old core version.	olivier.girard	5325d 17h	/openmsp430/
37		olivier.girard	5325d 17h	/openmsp430/
36	Remove old core version.	olivier.girard	5325d 18h	/openmsp430/
35	Update documentation to reflect the latest Verilog changes.	olivier.girard	5325d 18h	/openmsp430/
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5325d 19h	/openmsp430/
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5325d 20h	/openmsp430/
32	Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory.	olivier.girard	5327d 16h	/openmsp430/
31	Update documentation (new Altera FPGA project + diverse minor updates)	olivier.girard	5327d 17h	/openmsp430/