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[/] [openmsp430/] [trunk/] [core/] - Rev 143

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95 Update some test patterns for the additional simulator supports. olivier.girard 4891d 04h /openmsp430/trunk/core/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4891d 04h /openmsp430/trunk/core/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4895d 05h /openmsp430/trunk/core/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4918d 01h /openmsp430/trunk/core/
85 Diverse RTL cosmetic updates. olivier.girard 4918d 03h /openmsp430/trunk/core/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4923d 04h /openmsp430/trunk/core/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4972d 11h /openmsp430/trunk/core/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4984d 05h /openmsp430/trunk/core/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4989d 03h /openmsp430/trunk/core/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5071d 04h /openmsp430/trunk/core/

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