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[/] [openmsp430/] [trunk/] [core/] - Rev 210

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138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4432d 00h /openmsp430/trunk/core/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4463d 15h /openmsp430/trunk/core/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4476d 15h /openmsp430/trunk/core/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4484d 14h /openmsp430/trunk/core/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4560d 14h /openmsp430/trunk/core/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4632d 15h /openmsp430/trunk/core/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4736d 16h /openmsp430/trunk/core/
115 Add linker script example. olivier.girard 4761d 16h /openmsp430/trunk/core/
112 Modified comment. olivier.girard 4769d 15h /openmsp430/trunk/core/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4770d 15h /openmsp430/trunk/core/

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