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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] - Rev 186

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Rev Log message Author Age Path
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4892d 06h /openmsp430/trunk/core/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4892d 08h /openmsp430/trunk/core/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4897d 09h /openmsp430/trunk/core/rtl/verilog/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4958d 09h /openmsp430/trunk/core/rtl/verilog/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5045d 09h /openmsp430/trunk/core/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5072d 10h /openmsp430/trunk/core/rtl/verilog/
67 Added 16x16 Hardware Multiplier. olivier.girard 5219d 17h /openmsp430/trunk/core/rtl/verilog/
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5219d 21h /openmsp430/trunk/core/rtl/verilog/
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5251d 08h /openmsp430/trunk/core/rtl/verilog/
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5253d 06h /openmsp430/trunk/core/rtl/verilog/

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