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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] - Rev 191

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Rev Log message Author Age Path
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4883d 09h /openmsp430/trunk/core/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4895d 10h /openmsp430/trunk/core/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4918d 06h /openmsp430/trunk/core/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4918d 08h /openmsp430/trunk/core/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4923d 09h /openmsp430/trunk/core/rtl/verilog/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4984d 10h /openmsp430/trunk/core/rtl/verilog/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5071d 09h /openmsp430/trunk/core/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5098d 10h /openmsp430/trunk/core/rtl/verilog/
67 Added 16x16 Hardware Multiplier. olivier.girard 5245d 17h /openmsp430/trunk/core/rtl/verilog/
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5245d 21h /openmsp430/trunk/core/rtl/verilog/

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