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[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 167

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94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4869d 00h /openmsp430/trunk/core/sim/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4873d 01h /openmsp430/trunk/core/sim/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4895d 22h /openmsp430/trunk/core/sim/
85 Diverse RTL cosmetic updates. olivier.girard 4896d 00h /openmsp430/trunk/core/sim/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4950d 08h /openmsp430/trunk/core/sim/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4962d 01h /openmsp430/trunk/core/sim/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4967d 00h /openmsp430/trunk/core/sim/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5049d 01h /openmsp430/trunk/core/sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5074d 02h /openmsp430/trunk/core/sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5076d 02h /openmsp430/trunk/core/sim/

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