URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 178

Rev	Log message	Author	Age	Path
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4847d 07h	/openmsp430/trunk/core/sim/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4851d 06h	/openmsp430/trunk/core/sim/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4851d 07h	/openmsp430/trunk/core/sim/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4855d 07h	/openmsp430/trunk/core/sim/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4878d 04h	/openmsp430/trunk/core/sim/
85	Diverse RTL cosmetic updates.	olivier.girard	4878d 06h	/openmsp430/trunk/core/sim/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4932d 14h	/openmsp430/trunk/core/sim/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4944d 07h	/openmsp430/trunk/core/sim/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4949d 06h	/openmsp430/trunk/core/sim/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5031d 07h	/openmsp430/trunk/core/sim/