URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 191

Rev	Log message	Author	Age	Path
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	4865d 10h	/openmsp430/trunk/core/sim/
99	Small fix for CVER simulator support.	olivier.girard	4869d 10h	/openmsp430/trunk/core/sim/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4869d 10h	/openmsp430/trunk/core/sim/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4873d 10h	/openmsp430/trunk/core/sim/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4873d 10h	/openmsp430/trunk/core/sim/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4877d 11h	/openmsp430/trunk/core/sim/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4900d 08h	/openmsp430/trunk/core/sim/
85	Diverse RTL cosmetic updates.	olivier.girard	4900d 10h	/openmsp430/trunk/core/sim/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4954d 17h	/openmsp430/trunk/core/sim/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4966d 11h	/openmsp430/trunk/core/sim/