URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 138

Rev	Log message	Author	Age	Path
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4971d 15h	/openmsp430/trunk/core/sim/rtl_sim/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5053d 16h	/openmsp430/trunk/core/sim/rtl_sim/
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5078d 16h	/openmsp430/trunk/core/sim/rtl_sim/
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5080d 17h	/openmsp430/trunk/core/sim/rtl_sim/
67	Added 16x16 Hardware Multiplier.	olivier.girard	5228d 00h	/openmsp430/trunk/core/sim/rtl_sim/
65	Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1.	olivier.girard	5238d 14h	/openmsp430/trunk/core/sim/rtl_sim/
58	Update the debug hardware breakpoint verification patterns to reflect the latest design updates.	olivier.girard	5261d 13h	/openmsp430/trunk/core/sim/rtl_sim/
55	Add a "sandbox" test pattern to play around with the simulation :-P	olivier.girard	5266d 15h	/openmsp430/trunk/core/sim/rtl_sim/
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5266d 17h	/openmsp430/trunk/core/sim/rtl_sim/
37		olivier.girard	5295d 15h	/openmsp430/trunk/core/sim/rtl_sim/