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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 192

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102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4928d 11h /openmsp430/trunk/core/sim/rtl_sim/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4928d 13h /openmsp430/trunk/core/sim/rtl_sim/
99 Small fix for CVER simulator support. olivier.girard 4932d 13h /openmsp430/trunk/core/sim/rtl_sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4932d 13h /openmsp430/trunk/core/sim/rtl_sim/
95 Update some test patterns for the additional simulator supports. olivier.girard 4936d 13h /openmsp430/trunk/core/sim/rtl_sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4936d 13h /openmsp430/trunk/core/sim/rtl_sim/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4940d 14h /openmsp430/trunk/core/sim/rtl_sim/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4963d 10h /openmsp430/trunk/core/sim/rtl_sim/
85 Diverse RTL cosmetic updates. olivier.girard 4963d 12h /openmsp430/trunk/core/sim/rtl_sim/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5017d 20h /openmsp430/trunk/core/sim/rtl_sim/

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