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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 192

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Rev	Log message	Author	Age	Path
95	Update some test patterns for the additional simulator supports.	olivier.girard	4871d 11h	/openmsp430/trunk/core/sim/rtl_sim/src/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4875d 12h	/openmsp430/trunk/core/sim/rtl_sim/src/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4898d 08h	/openmsp430/trunk/core/sim/rtl_sim/src/
85	Diverse RTL cosmetic updates.	olivier.girard	4898d 10h	/openmsp430/trunk/core/sim/rtl_sim/src/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4964d 12h	/openmsp430/trunk/core/sim/rtl_sim/src/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5051d 11h	/openmsp430/trunk/core/sim/rtl_sim/src/
67	Added 16x16 Hardware Multiplier.	olivier.girard	5225d 19h	/openmsp430/trunk/core/sim/rtl_sim/src/
58	Update the debug hardware breakpoint verification patterns to reflect the latest design updates.	olivier.girard	5259d 08h	/openmsp430/trunk/core/sim/rtl_sim/src/
55	Add a "sandbox" test pattern to play around with the simulation :-P	olivier.girard	5264d 10h	/openmsp430/trunk/core/sim/rtl_sim/src/
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5293d 12h	/openmsp430/trunk/core/sim/rtl_sim/src/

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