URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] - Rev 82

Rev	Log message	Author	Age	Path
30	Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution).	olivier.girard	5340d 10h	/openmsp430/trunk/fpga/
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5340d 10h	/openmsp430/trunk/fpga/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5348d 18h	/openmsp430/trunk/fpga/
27	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5348d 18h	/openmsp430/trunk/fpga/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5348d 18h	/openmsp430/trunk/fpga/
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5438d 16h	/openmsp430/trunk/fpga/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5438d 16h	/openmsp430/trunk/fpga/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5459d 14h	/openmsp430/trunk/fpga/
20	added some SVN ignore patterns. small update to html documentation	olivier.girard	5485d 08h	/openmsp430/trunk/fpga/
16	Updated header with SVN info	olivier.girard	5485d 10h	/openmsp430/trunk/fpga/