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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] - Rev 221

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Rev Log message Author Age Path
136 Update all FPGA projects with the latest core version. olivier.girard 4478d 12h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4491d 13h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4575d 13h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
112 Modified comment. olivier.girard 4784d 13h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4785d 13h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4841d 11h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4856d 12h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4860d 14h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4865d 12h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4866d 13h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/

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