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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] - Rev 205

Rev	Log message	Author	Age	Path
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4868d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4882d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4905d 07h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
85	Diverse RTL cosmetic updates.	olivier.girard	4905d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4910d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4956d 10h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4959d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4959d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/