URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 128

Rev	Log message	Author	Age	Path
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5305d 22h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
40	Minor updates.	olivier.girard	5334d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5334d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
37		olivier.girard	5334d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
36	Remove old core version.	olivier.girard	5334d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5345d 04h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5345d 04h	/openmsp430/trunk/fpga/diligent_s3board/
25	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5435d 02h	/openmsp430/trunk/fpga/diligent_s3board/
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5435d 02h	/openmsp430/trunk/fpga/diligent_s3board/
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5456d 00h	/openmsp430/trunk/fpga/diligent_s3board/