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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 199

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106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4844d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4859d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4863d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4869d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4873d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4877d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4900d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
85 Diverse RTL cosmetic updates. olivier.girard 4900d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4905d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4966d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/

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