OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] - Rev 167

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Update the FPGA projects with the latest core design updates. olivier.girard 5333d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5338d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
37 olivier.girard 5367d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
36 Remove old core version. olivier.girard 5367d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5377d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5377d 16h /openmsp430/trunk/fpga/diligent_s3board/rtl/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5488d 11h /openmsp430/trunk/fpga/diligent_s3board/rtl/
16 Updated header with SVN info olivier.girard 5514d 07h /openmsp430/trunk/fpga/diligent_s3board/rtl/
3 update FPGA inc file to match the CORE version olivier.girard 5548d 19h /openmsp430/trunk/fpga/diligent_s3board/rtl/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5549d 07h /openmsp430/trunk/fpga/diligent_s3board/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.